1. Field of the Invention
The present invention relates to a semiconductor memory device and, more specifically, to a highly integrated structure of a DRAM having a so called cylindrical stacked capacitor and to a manufacturing method thereof.
2. Description of the Background Art
Developments have been made in the field of semiconductor memory devices, especially in dynamic random access memories (DRAMs) to increase degree of integration and to reduce the size of device structures, so as to realize increase in memory capacity and to realize higher responsiveness.
FIG. 5 is a block diagram of a DRAM. Referring to FIG. 5, a schematic structure of a DRAM will be described. Generally, a DRAM includes a memory cell array as a memory region storing pieces of memory information, and a peripheral circuitry necessary for external input/output. More specifically, a DRAM 50 comprises a memory cell array 51 for storing data signals of memory information; a row and column address buffer 52 for receiving external address signals for selecting a memory cell constituting a unit memory circuit; a row decoder 53 and a column decoder 54 for designating the memory cell by decoding the address signals; a sense refresh amplifier 55 for amplifying and reading a signal stored in the designated memory cell; a data in buffer 56 and a data out buffer 57 for inputting/outputting data; and a clock generator 58 for generating a clock signal.
The memory cell array 51 occupying a large area on a semiconductor chip comprises a plurality of memory cells each storing unit memory information. The memory capacity of the DRAM is defined by the number of memory cells arranged in the memory cell array 51. Therefore, various improvements have been done to make smaller the structure of a MOS transistor and a capacitor forming the memory cell so as to increase degree of integration in the memory cell array 51. For example, in the MOS transistor constituting the memory cell, channel length is shortened to make small the structure of the element, and by improving element isolating structure, spaces between elements have been made smaller. However, capacitors have been obstructive to the reduction in size of structures, since the capacitor capacity is proportional to the area between opposing electrodes, and it is necessary to ensure a capacity larger than a prescribed amount for reliability of memory operation as a memory device. Accordingly, capacitor structure has been improved to make the cell structure of the memory cell smaller while ensuring capacitor capacity, resulting in a so called cylindrical stacked capacitor cell.
FIG. 6 is a cross sectional structure of a DRAM disclosed in, for example, "A CROWN TYPE STACKED CAPACITOR CELL FOR A 1.5V OPERATION 64MDRAM", Kaga et al, Proceedings of 37th Applied Physics Association Conference, 2nd volume, P582. FIG. 6 shows a memory cell portion and a peripheral circuitry portion. The memory cell comprises one transfer gate transistor 3 and one capacitor 10. The transfer gate transistor 3 has a pair of source.cndot.drain.regions 6a, 6b formed on a surface of a silicon substrate 1, and gate electrodes (word lines) 4b, 4c formed on the surface of the silicon substrate 1 between the source.cndot.drain regions 6a, 6b with a gate insulating layer 5 posed therebetween. Above a field oxide film 2 covering a prescribed region on the surface of the silicon substrate 1, word lines 4a and 4d extending to adjacent memory cells are formed. The surfaces of the gate electrodes (word lines) 4a to 4d are covered with a first insulating layer 20.
A bit line 15 is connected to one of the source.cndot.drain regions 6a of the transfer gate transistor 3. The bit line 15 is formed of a two-layered polycrystalline silicon layer. A portion which is to be connected to one of the source.cndot.drain regions 6a of the transfer gate transistor 3 is formed by selective CVD method. The surface of the bit line 15 is covered with a second insulating layer 21.
The capacitor 10 has a stacked structure of a lower electrode (storage node) 11, a dielectric layer 12 and an upper electrode (cell plate) 13. The lower electrode 11 has a base portion 11a extending over the gate electrodes 4a to 4d or the bit line 15, and an upright wall portion 11b extending vertically upward. A portion of the lower electrode 11 is connected to the other one of the source.cndot.drain regions 6b of the transfer gate transistor 3 through a polycrystalline silicon layer embedded in the contact portion. A capacitor portion of the capacitor 10 is constituted by the surface of the base portion 11a and inner and outer surfaces of the wall portion 11b of the lower electrode 11. Since the wall portion 11b can be utilized as the capacitor portion, the capacitor capacity can be increased without increasing the planar area of occupation of the capacitor.
The peripheral circuitry such as the input/output buffer has a number of MOS transistors 30 as structural components. A MOS transistor 30 has a pair of source.cndot.drain regions 33, 33, and a gate electrode 31 formed on a gate insulating layer 32. A first insulating layer 20 surrounds the gate electrode 31. An interconnection layer 18 is connected to the source.cndot.drain regions 33, 33 through a contact formed in an interlayer insulating layer 22.
However, in conventional DRAM having a cylindrical stacked capacitor, large steps have been generated at surfaces of the insulating layers and interconnection layers, due to the heights of functional elements between the memory cell region and the peripheral circuitry portion. During manufacturing the DRAM, the MOS transistors 3 and 30 in the memory cell region and the peripheral circuitry are formed simultaneously by approximately the same processes, and then the capacitor 10 in the memory cell portion is manufactured. In this step, the capacitor 10 is formed high above the surface of the silicon substrate in the memory region, while the MOS transistor 30 is formed in the peripheral circuitry. Therefore, when an interlayer insulating layer 22 is formed on the entire surface in the succeeding step, the position of the surfaces in the memory cell region and the peripheral circuitry region is very much different, causing a large step. Consequently, in the succeeding step of lithography, precision in patterning is degraded if the step is larger than focal depth of an exposure apparatus, making it difficult to provide fine and small structures. For example, when the interconnection layer 18 is to be connected to the source.cndot.drain regions 33 in the peripheral circuitry, precision in registration may be degraded, and in order to prevent the degradation, diffusion width of the source.cndot.drain regions 33 must be set larger. This prevents reduction in size of the transistor.